1. Field of the Invention
This invention relates to integrated circuit memory devices. More particularly this invention relates to circuits and devices for simultaneous storing and/or retrieving of digital data to and from integrated circuit memory. Even more particularly, this invention relates to simultaneous reading and programming of non-volatile integrated circuit memory or flash memory.
2. Description of Related Art
Non-volatile memories, especially Flash memories, have been widely used in various electronic applications such as computers, hand-held computing and control devices, communication devices, and consumer products. Due to its characteristic of non-volatility and on-system re-programmability, the flash memories are suitable to store both the program code and data code for a system. However, flash memory has its own disadvantage. Compared with volatile memories such as dynamic random access-memories and static random access memories, flash memories require a relative long period of time in processing a program/erase or xe2x80x98writexe2x80x99 operation. It typically takes several microseconds to seconds to write the data. During this time period, the whole memory is occupied and no other memory operations such as a read may be performed. Therefore, a xe2x80x98simultaneous read and write operationxe2x80x99 is highly demanded for flash memory.
An example of a simultaneous read and write operation for a flash memory is shown in U.S. Pat. No. 6,088,264 (Hazen et al.). The memory array contains more than two individual arrays and each array can independently perform read or write operations. Therefore, the data stored in one array can be read while the other array is doing the write operation. Each array of Hazen et al. requires additional decoder circuits, data buses, and control circuits to perform the simultaneous read and write operation. The extra area consumed, thus, limits the number of the arrays being used. Because the number of arrays is limited, each array is generally denser. This diminishes the amount of data that can be simultaneously read and/or written. When one array is being programmed or written to, the whole is array is unavailable being read.
U.S. Pat. No. 5,847,998 (Van Buskirk), disclosed another approach to enable arrays having a much smaller size for simultaneous read and write operation. It directly divided the array into several small-size blocks, such as 512 kb per block, and enables each block to be simultaneously read or programmed. Unfortunately, this approach can be only used for a flash memory having a xe2x80x98NORxe2x80x99 structured array only. It cannot be used for any other flash memory array structures such as flash memories having an xe2x80x98ANDxe2x80x99 array structure, because the cell operation and the bias conditions for the NOR array and the AND array are different.
It is well known in the art that flash memories have different array structures, and each array structure has its own features and characteristics. These array structures can be basically fallen into two categories, the xe2x80x98NOR-typexe2x80x99 array, as illustrated in U.S. Pat. No. 6,301,153 (Takeuchi et al.) and the xe2x80x98NAND-typexe2x80x99 array, as illustrated in U.S. Pat. No. 6,288,944 (Kawamura). For the NOR-type array, the memory cells are connected to bit lines in parallel. The NAND-type array, on the other hand, connects the memory cells serially. Due to this major difference, the NOR-type array tends to provide faster read speed and thus the NOR-type array dominates the high-speed application market. The NAND-type array tends to have smaller cell size. Due to its serial structure, the NAND-type, thus, dominates the low-cost, slow-speed, higher-density market.
The conventional NOR-type array includes several different structures as illustrated in Takeuchi et al. Takeuchi et al. illustrates the NOR, AND, and DINOR array structures. Other known structures include the Dual-String NOR and the OR. Each structure is an optimum solution for its own technology, and its own read, erase and program conditions and algorithm. The structures are further categorized according to the programming mechanism used. Only the NOR array and some Dual-String NOR arrays use Channel-Hot-Electron (CHE) injection in programming. All others use Fowler-Nordheim (FN) tunneling in programming. For this invention the NOR-type flash memory arrays that use Channel-Hot-Electron programming are termed xe2x80x98NOR-likexe2x80x99 arrays. The NOR-type arrays that use Fowler-Nordheim tunneling for programming are termed xe2x80x98AND-likexe2x80x99 array.
The conventional NOR-like array and the AND-like array structures of the prior art are not suitable for the simultaneous read and write (program/erase) operation. The simultaneous read and write operation is not possible because the array structures NOR-like array and the AND-like array cannot allow multiple blocks from being accessed, one for read and one for programming, at the same time. For example, FIG. 1 illustrates a conventional NOR array as an example of the NOR-like arrays.
The NOR structured flash memory is divided into multiple blocks 10 and 20. Each block 10 and 20 consists of memory cells M11, . . . , MN4, and M21, . . . , MM4. The control gates of each row of the memory cells M11, . . . , MN4, and M21, . . . , MM4 are connected together and to the word lines 41, 42, 43, and 44. The word lines 41, 42, 43, and 44 are connected to word line amplifier 40 to receive the word line control signals to cause selected rows of the memory cells M11, . . . , MN4, and M21, . . . , MM4 to be either read or written (programmed/erased).
Each column of the memory cells M1, . . . , MN4, and M21, . . . , MM4 of each array block 10 and 20 are interconnected by sub-bit lines or local bit lines 11, 12, 13, and 14 for array block 10 and local bit lines 21, 22, 23, and 24 for array block 20. The local bit lines 11, 12, 13, and 14 for array block 10 are connected respectively to the sources of the switch transistors Q1, Q2, Q3, and Q4. The drains of the switch transistors Q1, Q2, Q3, and Q4 are connected respectively to the global bit lines 61, 62, 63, and 64. The local bit lines 21, 22, 23, and 24 for array block 20 are connected respectively to the sources of the switch transistors Q5, Q6, Q7, and Q8. The drains of the switch transistors Q5, Q6, Q7, and Q8 are connected respectively to the global bit lines 61, 62, 63, and 64.
The global bit lines 61, 62, 63, and 64 are connected to the bit line amplifier 60 to receive the bit line control signals to cause the memory cells M11, . . . , MN4, and M21, . . . , MM4 to be either read or written (programmed/erased).
The encoded address signals 30 are received and decoded by the address decoder 30. The decoded address signals 34 are transferred to the word line amplifier 30 and the bit line amplifier 60. The decoded address signals provide the word line and bit line control signals to activate the desired memory cells M11, . . . , MN4, and M21, . . . , MM4 to be either read or written (programmed/erased). The read/write signal 56 and other timing and control signals (not shown) are received by the read/write control circuit 50 to provide the necessary timing and control signals 53 and 54 to the bit line amplifier 60 and the word line amplifier 40.
The gate select lines 51 and 52 are provided by the read/write control circuit 50 to activate the desired switch transistors Q1, Q2, Q3, and Q4 or the desired switch transistors Q5, Q6, Q7, and Q8. The selected switch transistors Q1, Q2, Q3, and Q4 or switch transistors Q5, Q6, Q7, and Q8 connect the local bit lines 11, 12, 13, and 14 for the array block 10 or the local bit lines 21, 22, 23, and 24 for array block 20 to the global bit lines 61, 62, 63, and 64.
The sources of each memory cell of each row of the memory cells M11, . . . , MN4, and M21, . . . , MM4 are connected together and to the source lines 71, 72, 73, and 74. The source lines 71, 72, 73, and 74 are connected to the sense amplifier 70 to detected the digital data read from the memory cells of a selected row of the memory cells M11, . . . , MN4, and M21, . . . , MM4. The control signal line 55 provides the necessary timing and activation signals to appropriately generate the digital data at the output 76 of the source line amplifier 76.
The NOR flash memory array, as shown, is not suitable for a simultaneous read and write operation, because of the array structure. When the array block 10 is selected, the select transistors (Q1-Q4) are all turned on by the control signal present at the gate select line 51, and all the global bit lines 61, 62, 63, and 64 are connected to the local bit lines 11, 12, 13, and 14. The local bit lines 21, 22, 23, and 24 of the second array block 20 will not be able to be read from or written to through the global bit lines 61, 62, 63, and 64, because all the global bit lines 61, 62, 63, and 64 are already connected to the local bit lines 11, 12, 13, and 14 of the first array block 10.
second example, as shown in FIG. 2 illustrates a conventional AND array as an example of the AND-like array. The structure of the AND array is similar to the NOR array of FIG. 1 except there is a second set of local bit lines 15, 16, 17, and 18 for the first array block 10 and a second set of local bit lines 25, 26, 27, and 28 for the first array block 20. The second set of local bit lines 15, 16, 17, and 18 of the first array block 10 and a second set of local bit lines 25, 26, 27, and 28 of the first array block 20 are respectively connected to the drains of the switch transistors Q1b, Q2b, Q3b, Q4b and the switch transistors Q5b, Q6b, Q7b, Q8b. The sources of the switch transistors Q1b, Q2b, Q3b, Q4b and the switch transistors Q5b, Q6b, Q7b, Q8b to the source lines 71 and 74.
The encoded address signal 32 is decoded by the address decoder 30 to produce the decoded address signal 34 that is the input to the word line amplifier 40, the read/write control circuit 50, and the bit line amplifier 60 to select the desired memory cells M11, . . . , MN4, and M21, . . . , MM4 for either reading or writing. The word line amplifier 40 selects the word line 41, 42, 43, and 44 containing the desired memory cells M1, . . . , MN4, and M21, . . . , MM4. The bit line amplifier 60 conditions the global bit lines 61, 62, 63, and 64 to contain the bit line signals to read or write (program/erase) the desired memory cells M11, . . . , MN4, and M21, MM4. The gate select lines 51 and 52 are selectively activated to connect the connect the local bit lines 11, 12, 13, and 14 for the array block 10 or the local bit lines 21, 22, 23, and 24 for array block 20 to the global bit lines 61, 62, 63, and 64. The gate select lines 58 and 59 are selectively activated to connect the local bit lines 15, 16, 17, and 18 for the array block 10 or the local bit lines 25, 26, 27, and 28 for array block 20 to the source lines 71 and 74.
The structure as shown will allow only one array block 10 or 20 to be selected. Since all the local bit lines 15, 16, 17, and 18 for the array block 10 or the local bit lines 25, 26, 27, and 28 for array block 20 are connected through the switch transistors Q1b, Q2b, Q3b, Q4b and the switch transistors Q5b, Q6b, Q7b, Q8b to the source lines 71 and 74, only one of the cells of the selected array block is read from or programmed.
As is known, the entire block may be erased simultaneously.
The AND array, as described, is not suitable for the simultaneous read and write operation because of the array structure. When the first array block 10 is selected, the switch transistors Q1b, Q2b, Q3b, Q4b are all turned on by the control signal present on the gate select line 51, and all the local bit lines 11, 12, 13, and 14 for the array block 10 are connected to the global bit lines 61, 62, 63, and 64. The local bit lines 21, 22, 23, and 24 for array block 20 will not be able to read from or written to through the global bit lines 61, 62, 63, and 64 because all global bit lines 61, 62, 63, and 64 are already connected to the local bit lines 11, 12, 13, and 14 for the array block 10.
U.S. Pat. No. 5,847,998 (Van Buskirk) discloses a NOR-array structured flash memory capable of performing simultaneous read and write operations. The global bit lines are separated into two groups, xe2x80x98read bit linesxe2x80x99 and xe2x80x98write bit linesxe2x80x99. Through the appropriate selection of switch transistors, local bit lines that are selected for read are connected to the global read bit lines, and the local lines that are selected for write are connected to the global write bit lines. Meanwhile, all the deselected local lines remain disconnected to be floating. However, this approach can be only applied to the NOR-like array only and is not applicable to AND-like array, because of differences in the cell operations, bias conditions, and sector organization of the NOR-like array versus the AND-like array.
To contrast the write operations of the NOR-like array and the AND-like array, the deselected local bit lines of the NOR-like array are disconnected to be floating. The NOR-like array uses channel-hot-electron (CHE) injection in programming, which requires a relatively large current, e.g. 500 uA, flowing through the memory cell channel. When deselected local bit lines are floating, the channel current is interrupted and automatically prevents the cells being programmed. Conversely, the AND-like array uses Fowler-Nordheim (FN) tunneling in programming. For this mechanism, when programming, a high electric field is applied across the tunnel oxide layer underneath the floating gate, so the high field will cause the electron to tunnel through the thin tunnel oxide. To inhibit the tunneling, the deselected bit lines have an appropriate middle-high voltage in order to cancel the electric field. Therefore, for AND-like array, during the write operation, both the selected and deselected bit lines have different voltages applied to the local bit lines. If there is no biasing voltage to cancel the electric field, the deselected local bit lines will be disturbed and cause the data loss from the deselected local bit lines. More detailed descriptions of the operations and program conditions for the NOR array and the AND array, are illustrated by U.S. Pat. No. 5,126,808 (Montalvo et al.) and U.S. Pat. No. 6,072,722 (Hirano) respectively. The problem of program-disturb associated with the AND-like array is discussed in more detail in U.S. Pat. No. 6,009,016 (Ishii et al.).
The NOR-like array typically cannot program a large number of the cells at one time because of the relatively high current required during programming. Thus, typically flash memories are programmed one byte at one time. In contrast, the AND-like array uses Fowler-Nordheim programming, which requires low programming current that is typically approximately 10 pA per cell. Thus, the AND-like array typically is able to program one page (e.g. 128b to 1024b) at one time.
Van Buskirk, as structured, is not applicable to the AND-like array because, as discussed above, the AND-like array requires the deselected local bit lines to be biased to prevent the disturb of the programmed digital data. Further, Van Buskirk cannot allow simultaneous writing of multiple array blocks because of the large current requirements.
U.S. Pat. No. 5,748,538 (to Lee et al. and assigned to the same assignee as the present invention) discloses a flash memory array referred to as an OR array, which according to the definition is included in the AND-like array category. The fundamental structure of the array is as shown in FIG. 2 except for the organization of the switching transistors that selectively connect the memory cells M11, . . . , MN4, and M21, . . . , MM4 to the global bit lines 61, 62, 63, 64 and 65. The first set of local bit lines 11, 12, 13, and 14 for array block 10 are connected respectively to the sources of the switch transistors Q1a, Q2a, Q3a, and Q4a. The drain of the switch transistors Q1a is connected to the global bit line 61. The drains of the switch transistors Q2a and Q3a are connected to the global bit line 63. The drain of the switch transistor Q4a is connected to the global bit lines 65. The local bit lines 21, 22, 23, and 24 for array block 20 are connected respectively to the sources of the switch transistors Q5a, Q6a Q7a, and Q8a. The drain of the switch transistors Q5a is connected to the global bit line 61. The drains of the switch transistors Q6a and Q6a are connected to the global bit line 63. The drain of the switch transistor Q7a is connected to the global bit lines 65. The second set of local bit lines 15, 16, 17, and 18 for array block 10 are connected respectively to the drains of the switch transistors Q1b, Q2b, Q3b, and Q4b. The sources of the switch transistors Q1b and Q2b are connected to the global bit line 62. The sources of the switch transistor Q3b and Q4b is connected to the global bit line 64. The local bit lines 21, 22, 23, and 24 for array block 20 are connected respectively to the drains of the switch transistors Q5b, Q6b, Q7b, and Q8b. The sources of the switch transistors Q5b and Q6b are connected to the global bit line 62. The sources of the switch transistor Q7b and Q8b is connected to the global bit line 64.
The global bit lines 61, 62, 63, 64 and 65 are connected to the bit line amplifier 60 and the sense amplifier 70. The bit line amplifier 60 conditions the bit lines to perform the appropriate read or write (program/erase) operation to the desired memory cells M11, . . . , MN4, and M21, . . . , MM4. The memory cells M11, . . . , MN4, and M21, . . . , MM4 when appropriately connected to through the switch transistors Q1a, Q2a, Q3a, and Q4a; Q5a, Q6a, Q7a, and Q8a; Q1b, Q2b, Q3b, and Q4b; and Q5b, Q6b, Q7b, and Q8b to the global bit lines 61, 62, 63, 64 and 65 are able to transfer the digital data to the sense amplifier 70. The digital data is then reconstructed in the sense amplifier 70 and transferred to the data output bus 76.
The gate control line 51a is connected to the gates of the switch transistors Q1a and Q3a. The gate control line 58a is connected to the gates of the switch transistors Q2a and Q4a. The gate control line 51b is connected to the gates of the switch transistors Q1b and Q3b. The gate control line 58b is connected to the gates of the switch transistors Q2b and Q4b. The gate control line 52a is connected to the gates of the switch transistors Q5a and Q7a. The gate control line 59a is connected to the gates of the switch transistors Q6a and Q8a. The gate control line 52b is connected to the gates of the switch transistors Q5b and Q7b. The gate control line 59b is connected to the gates of the switch transistors Q6b and Q8b. 
The local bit lines 11, 12, 13, and 14 for array block 10 and the local bit lines 21, 22, 23, and 24 for array block 20 are designated as two groupsxe2x80x94an even group and odd group. During the read or write operation, only one group of the local bit lines will be accessed at any one time. For example, the local bit lines 11, 12, 13, and 14 for array block 10 are separated into the even local bit lines 12 and 14 and the odd local bit lines 11 and 13. In a read operation, the odd local bit lines 11 and 13 are connected to the global bit lines 61 and 63, when the select transistors Q1a and Q3a are turned on by the control signal 51a. Meanwhile, the select transistors Q2a and Q4a for the even local bit lines 12 and 14 are turned off by the control signal 61a to disconnect the even local bit lines 12 and 14 from the odd global bit lines 63 and 65. In the read operation, the even global bit lines 62 and 64 are biased by the sense amplifier 70 to act as virtual ground for the selected cells. Thus, the even global bit lines 62 and 64 are connected to the source lines of the odd local bit lines 15 and 17 by turning on the select transistors Q1b and Q3b. Meanwhile, the select transistors Q2b and Q4b for the even local bit lines 16 and 18 are turned off to disconnect the source lines of the even local bit lines 16 and 18 from the even global bit lines 62 and 64. The activation of the switch transistors as described enables the odd local bit lines 11 and 13 to be read while remaining the even local bit lines 12 and 14 remain disconnected to be floating. The even global bit lines 62 and 64 are similarly read while the odd local bit lines 11 and 13 are disconnected by appropriately activating the switching transistors Q1a, Q2a, Q3a and Q1b, Q2b, Q3b, and Q4b. As can be seen, the array block 20 is not addressable during any operation within the array block 10. Thus is becomes obvious that there can be not simultaneous reading and/or writing to the multiple array blocks 10 or 20.
An objective of this invention is to provide a integrated circuit memory capable of simultaneous reading and/or writing of digital data to multiple memory cells within the integrated circuit memory.
Another object is to provide a non-volatile integrated circuit memory capable of simultaneous reading and/or writing of digital data to multiple memory cells within the integrated circuit memory.
Further another object of this invention is to provide a non-volatile integrated circuit memory having an AND-like array structure capable of simultaneous reading and writing of digital data to multiple memory cells within the integrated circuit memory.
To accomplish at least one of these and other objects, a integrated circuit memory array that allows simultaneous storage and retrieval of digital data includes a plurality of array blocks of memory cells. The memory cells within an array block of memory cells are arranged in columns and rows. A plurality of block bit lines is in communication with each array block of memory cells such that each block bit line interconnects the memory cells of one column of memory cells within one array block. A plurality of word lines is in communication with each array block of memory cells such that each word line interconnects the memory cells of one row within one array block.
The integrated circuit memory further includes a plurality of global bit lines in communication with the array blocks to select a column of the array blocks and to transfer the digital data from and to the array blocks. A bit line selector is connected between the plurality of global bit lines and the plurality of block bit lines to selectively connect the plurality of global bit lines to the block bit lines. An array controller is connected to the plurality of word lines, the plurality of bit lines and the bit line selector to control selection of a row of a block of the array, control transfer of the digital data from selected global bit lines to selected block bit lines, control transfer of the digital data to other selected global bit lines from other selected bit lines to allow simultaneous transfer of the digital data from and to selected memory cells.
The integrated circuit memory array further has sense amplifiers connected to each of the global bit lines to reconstruct the stored digital data. Each global bit line is divided into two portions. The first portion is connected to the array controller to provide select signals to selectively activate one column of the memory array. The second portion is connected to the sense amplifier to transfer retained digital data to a selected sense amplifier.
The bit line selector consists of a first plurality of switches and a second plurality of switches. Each switch of the first plurality of switches has a first terminal connected to one of the plurality of global bit lines, a second terminal connected to one of the block bit lines, and a control terminal connected to receive control signals from the array controller. Each switch of the second plurality of switches has a first terminal connected to a second end of one of the block bit lines, a second terminal connected to the second portion of one of the plurality of global bit lines, and a control terminal connected to receive control signals from the array controller. Each switch is a MOS transistor with the first terminal being a drain of the MOS transistor, the second terminal being a source of the MOS transistor and the control terminal being a gate of the MOS transistor.